Power amplifiers are sized for peak efficiency at maximum power out. Maximum power out is defined by the specification. Efficiency is power out divided by DC power. DC power remains about the same through operation. Efficiency drops as a function of the output power. Therefore, a drop in output power of only few [dB] can result in about a 50% drop in efficiency, or even more.
FIG. 1(a) shows a typical power amplifier 10 top level diagram including a low noise input amplifier 18, one or more intermediary driver stages 16, the last driver 14, the high power output stage 12, biasing and miscellaneous circuits 19, and the output power level control circuit 100.
In power amplifiers 10 it is the last stage 12 that has the largest power dissipation, followed by the last driver stage 14. FIG. 1(b) shows a typical pie-chart of the total power dissipation and the contribution of each major power amplifier system building block. The power dissipation is by far dominated by the contribution of the last two stages 11 and 13 from the signal path. Therefore, any technique of improving the power amplifier system efficiency has two deal with these two last stages.
A typical plot of a power amplifier efficiency versus the output power level is shown in FIG. 2(a). The efficiency grows steeply in the last few [dB] of the output power level, reaching its peak value (PAE Max) at, or around the peak output power level (rated power level Pmax). However, if we analyze the amount of time that most power amplifier systems operate at the peak output level in a real-life communication application (e.g. GSM type wireless telephony), we may conclude that most of the time the power amplifier system operates away from the peak power level. FIG. 2(b) shows an example of the output signal probability density function, which gives the percentage of time the power amplifier system spends at each power level ranging from the minimum (Pmin) to the maximum (Pmax) level in a generic application. In many cases most of the time the power amplifier system operates around an average or median power (Pave) which is several [dB] lower than the peak value.
Since the efficiency of traditional power amplifier systems drops very sharply from the peak value even for a few [dB] away (e.g. 10% of efficiency loss for each [dB] of lower power level), the effective efficiency of the power amplifier system in real life operation conditions is significantly lower than its peak efficiency value. As an example, if a traditional PA has a peak efficiency of 50% at peak power level, in real applications its “average” efficiency may be as low as 30% or even lower. This results in a much lower battery time, which is one of the most important customer metrics. Optimizing the power amplifier system performance for a larger battery time requires a power amplifier system with much higher efficiency at backed-off power levels. This is the main objective of this invention.
One established technique (Doherty PA) that is widely used in the discrete power amplifier systems and the semi-integrated power amplifier systems to achieve a better efficiency at backed-off power level is to use two or more power amplifiers that have their output combined such that at maximum output power level both (all) stages are active, while at lower power levels (one or more) stages are turned off to improve efficiency. At lower power level (Pbackeoff) the efficiency achieves a second maximum since one power amplifier system stage is turned off and the other power amplifier system stage operates at peak power. Multiple maximums can be realized in the efficiency characteristic by combining more than 2 power amplifier system stages.
Another technique used in the past is power combining of several smaller size PAs. Such a technique needs transformers (baluns) or other hybrid components to perform the power combining.
The major drawback of the Doherty and power combining techniques is their poor integration level due to the needs of large-size transmission lines or transformers (baluns) to achieve the input signal splitting, and the output signal combining. The size constraint is very dramatic at lower operating frequency (e.g. 1 GHz). This prevents the full system integration and increases the size and cost.
By far the most popular power control technique for the saturated PAs is the drain or collector supply modulation using a constant feedback transfer. While this performs fine at peak output power levels, its efficiency performance at backed-off power levels is rather poor due to the large voltage drop and thus high power loss in the supply modulating device (regulator, DC-DC converter, or the like).
For the modern mobile battery operated transmitters and transceivers, such as cellular telephony handsets, it is very important to achieve a power amplifier that can provide the peak output power, while also ensuring a high efficiency at backed-off power levels, while all these features are achieved in a small footprint and at a low cost. A low cost and small size asks for a high level of integration, which cannot be realized with the existing PA technology.
It is the main object of this patent to describe a PA architecture and power control technique that is easy to integrate and which gives a high efficiency both at peak output power level and at backed-off power levels.